| 发明名称 |
Apparatus and Method for Power MOS Transistor |
| 摘要 |
A method comprises forming a first trench and a second trench, depositing a dielectric material in a lower portion of the first trench, depositing a gate electrode material in the second trench and an upper portion of the first trench, forming a first N+ region and a second N+ region through an ion implantation process, wherein the first N+ region and the second N+ region are on opposite sides of the first trench and forming an accumulation layer along a sidewall of the second trench. |
| 申请公布号 |
US2015064868(A1) |
申请公布日期 |
2015.03.05 |
| 申请号 |
US201414527488 |
申请日期 |
2014.10.29 |
| 申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Ng Chun-Wai;Chou Hsueh-Liang;Su Po-Chih;Liu Ruey-Hsin |
| 分类号 |
H01L29/66 |
主分类号 |
H01L29/66 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
providing a semiconductor device comprising:
a first trench comprising:
a dielectric layer formed in a lower portion of the first trench; anda first gate region formed in an upper portion of the first trench;a first N+ region and a second N+ region on opposite sides of the first trench; anda second trench adjacent to the second N+ region, wherein a gate electrode material is filled in the second trench; and forming accumulation layer along a sidewall of the second trench. |
| 地址 |
Hsin-Chu TW |
