发明名称 |
Multiplexed oscillators |
摘要 |
An integrated circuit device contains two oscillators to generate a first clock signal and a second clock signal. Along with comparing the frequencies of the first clock signal and the second clock signal, the integrated circuit device is configured to monitor whether or not each frequency is within the frequency tolerance range. The integrated circuit device selects an output clock signal from either of the first clock signal or the second clock signal according to results from comparing the frequencies of the first clock signal and the second clock signal and whether or not each of the first clock signal and the second clock signal are within the frequency tolerance range. |
申请公布号 |
US8970277(B2) |
申请公布日期 |
2015.03.03 |
申请号 |
US201314087201 |
申请日期 |
2013.11.22 |
申请人 |
Renesas Electronics Corporation |
发明人 |
Koazechi Shinichi;Kurokawa Tatsufumi |
分类号 |
H03K3/013;G01R23/00 |
主分类号 |
H03K3/013 |
代理机构 |
Sughrue Mion, PLLC |
代理人 |
Sughrue Mion, PLLC |
主权项 |
1. An integrated circuit device comprising:
a first oscillator that generates a first clock signal; a second oscillator that generates a second clock signal; a first frequency monitor unit that monitors whether or not the frequency of the first clock signal is within a specified frequency tolerance range, and generates a first clock normal signal showing whether or not the frequency of the first clock signal is within the frequency tolerance range; a second frequency monitor unit that monitors whether or not the frequency of the second clock signal is within the frequency tolerance range, and generates a second clock normal signal showing whether or not the frequency of the second clock signal is within the frequency tolerance range; a comparator circuit that compares the frequency of the first clock signal with the frequency of the second clock signal, and generates a selection signal that selects either of the first clock signal or the second clock signal in response to the results of the clock signal frequency comparison; and a selector configured to output an output clock signal selected from among the first clock signal and the second clock signal in response to the first clock normal signal, the second clock normal signal, and the selection signal. |
地址 |
Kanagawa JP |