发明名称 Semiconductor device and method for manufacturing the same
摘要 A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n+-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n+-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n+-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n+-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.
申请公布号 US8969150(B2) 申请公布日期 2015.03.03
申请号 US201414324632 申请日期 2014.07.07
申请人 Renesas Electronics Corporation 发明人 Katou Hiroaki;Moriya Taro;Kudou Hiroyoshi;Uchiya Satoshi
分类号 H01L29/78;H01L29/66 主分类号 H01L29/78
代理机构 Sughrue Mion, PLLC 代理人 Sughrue Mion, PLLC
主权项 1. A method for manufacturing a semiconductor device including a trench gate type field effect transistor and a diode which are formed in a semiconductor substrate, the method comprising the steps of: (a) preparing the semiconductor substrate; (b) after the step (a), forming a first trench and a second trench in the semiconductor substrate; (c) after the step (b), forming a gate electrode of the trench gate type field effect transistor in the first trench through a gate insulating film and forming a dummy gate electrode in the second trench through a dummy gate insulating film; (d) after the step (a), forming a first semiconductor region in the semiconductor substrate, the first semiconductor region of a first conductivity type; and (e) after the step (a), forming a second semiconductor region in the semiconductor substrate, the second semiconductor region having a second conductivity type opposite to the first conductivity type, wherein the second semiconductor region is planarly surrounded by the second trench, wherein a part of the first semiconductor region is located directly below the second semiconductor region and a PN junction is formed between the second semiconductor region and the part of the first semiconductor region located directly below the second semiconductor region, and thereby the diode is formed, and wherein the dummy gate electrode is electrically coupled to one of the first semiconductor region and the second semiconductor region.
地址 Kanagawa JP