| 摘要 |
<p>Methods of increasing the efficiency of memory resources within a processor 600 are described. In an embodiment, instead of including dedicated DSP (digital signal processing) indirect register resource (211, fig. 2) for storing data associated with DSP instructions, this data is stored in an allocated and locked region 606 within the cache 607 (e.g. L1 cache). The state of any cache lines which are used to store DSP data is then set to a write never state to prevent the data from being written back to memory(except upon a context switch (312, 316)). The size of the allocated region within the cache may be fixed or vary dynamically according to the amount of DSP data that needs to be stored and when no DSP instructions are being run, no cache resources are allocated for storage of DSP data. Also, the functionality of DSP access pipeline (214) is absorbed into the load-store pipeline 611. Two or more channels 608 may connect load-store pipeline 611 and cache 607. Cache 607 may be partitioned. Processor 600 may be a multithreaded processor having threads 602, 604 or single-threaded. The modified cache architecture may be used by other special instruction sets.</p> |
