发明名称 Error detection and reporting
摘要 System and method for detecting and reporting an error in communications with customer premise equipment. A preferred embodiment comprises monitoring the communications link between an access device and customer premise equipment located on customer premises. If a communications link fails, or some other condition occurs, an error signal is transmitted to the access network to notify downstream network elements of the error condition. In one embodiment, an access device is communicatively coupled to a demarcation device via an Ethernet link. If a loss of link occurs on the Ethernet link, an error signal, such as an alarm indicator signal, is transmitted through the network.
申请公布号 US8966052(B2) 申请公布日期 2015.02.24
申请号 US200410859463 申请日期 2004.06.02
申请人 Verizon Patent and Licensing Inc. 发明人 DelRegno Nick;Kotrla Scott R.;McDysan David E.;Bencheck Michael U.;Turlington Matthew W.;Hardin Ross S.;Schell Richard C.;Chiu Howard;Drake William
分类号 G06F15/16;H04M3/30;H04M3/10;H04L1/00;H04M3/08;H04M3/22 主分类号 G06F15/16
代理机构 代理人
主权项 1. An access device comprising: a processor; a first port configured for communicatively coupling to a demarcation device via an Ethernet link; a second port configured for communicatively coupling to an add/drop multiplexer (ADM) via a DS-3 communications link, wherein the ADM separates traffic on the DS-3 link from, and integrates onto, the Ethernet link; and a processing unit configured to monitor the first port and to generate an alarm signal on the second port when the processing unit detects that electrical connectivity has been lost due to a loss of the Ethernet link, wherein, the alarm signal is generated using an M-frame of a DS-3 frame, wherein the M-frame has seven M-subframes, each M-subframe has 680 bits divided into blocks 1 through 8, each comprised of an overhead bit and 84 payload bits, and wherein, when the alarm signal is generated, the overhead bit of block 1 of the first and second M-subframes is set to a logic “0”, the overhead bit of each of blocks three, five, and seven in each of the seven M-subframes is set to a logic “1”, and the 84 payload bits contained in each of the seven M-subframes are set to a repeating “10” bit pattern.
地址 Basking Ridge NJ US