发明名称 chip stack package
摘要 A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.
申请公布号 KR101494591(B1) 申请公布日期 2015.02.23
申请号 KR20070109698 申请日期 2007.10.30
申请人 发明人
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
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