Method And Apparatus For A Zero Voltage Processor

摘要

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

主权项

1. A system comprising:
a graphics processor; a wireless communication module; a memory controller; and a multi-core processor, the multi-core processor including:
a first processor core, the first processor core to save a state of the first processor core and to enter a mode in which the first processor core is powered off;a second processor core, the second processor core to save a state of the second processor core and to enter a mode in which the second processor core is powered off; anda cache memory, the cache memory to be powered when the first processor core is powered off; wherein the first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered, and the second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered.