DYNAMIC BURST LENGTH OUTPUT CONTROL IN A MEMORY

摘要

A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.

主权项

1. An apparatus comprising:
a command decoder configured to receive command information and produce a command indication in response to the command information; a holding circuit configured to capture and output a control signal at an output node in response to the command indication; and a plurality of latch circuits coupled in common to the output node of the holding circuit, each of the latch circuits being configured to latch the control signal in response to an assertion of an associated one of first enable signals, the first enable signals being asserted exclusively.