Memory controller

摘要

According to an embodiment, a memory controller includes: a coding unit that performs an error correction coding process for user data to generate first to n-th parities and performs the error correction coding process for each of the first to n-th parities to generate first to n-th external parities; and a decoding unit that performs an error correction decoding process using the user data, the first to n-th parities, and the first to n-th external parities. A generator polynomial used to generate an i-th parity is selected on the basis of a generator polynomial used to generate the first to (i−1)-th parities.

主权项

1. A memory controller that controls a non-volatile memory, comprising:
a coding unit that performs an error correction coding process for user data to generate first to n-th parities and performs the error correction coding process for each of the first to n-th parities to generate first to n-th external parities; a memory interface unit that controls writing and reading of the user data, the first to n-th parities, and the first to n-th external parities to and from the non-volatile memory; and a decoding unit that performs the error correction decoding process using the user data, the first to n-th parities, and the first to n-th external parities read from the non-volatile memory, wherein a generator polynomial used to generate the i-th parity (i is an integer equal to or greater than 1 and equal to or less than n) is selected based on a generator polynomial used to generate the first to (i−1)-th parities.