Systems, methods, and apparatus for memory cells with common source lines

摘要

Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.

主权项

1. A method comprising:
receiving a first voltage at a first transistor, the first transistor being coupled to a second transistor, the first transistor and second transistor being included in a first memory cell; receiving a second voltage at a third transistor, the third transistor being coupled to a fourth transistor, the third transistor and fourth transistor being included in a second memory cell, the first memory cell and the second memory cell being coupled to a common source line; receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor; and receiving a fourth voltage at a gate of the first transistor, the fourth voltage causing, via Fowler-Nordheim tunneling, a change in one or more electrical properties of a charge storage layer included in the first transistor.