Method and system for quantization-free and phase-dithered fractional-N generation for phase-locked-loops

摘要

A phased lock loop (PLL) including a retimer unit, rotator unit, and clock selection unit. The retimer unit is configured for sampling a divided clock generated by a divide-by-N unit with a plurality of phases of an oscillator clock generated by a ring oscillator to generate a plurality of phase shifted divide-by-N clocks. The rotator unit is configured for selectively rotating through the plurality of phase shifted divide-by-N clocks based on a constant phase shift interval, wherein the rotator unit controls a clock selection unit to produce a single output phase selected from a plurality of generated divide-by-N clock phases.

主权项

1. A phase locked loop system, comprising:
a retimer unit configured for sampling a divided clock generated by a divide-by-N unit with a plurality of phases of an oscillator clock generated by a ring oscillator to generate a plurality of phase shifted divide-by-N clocks; and a rotator unit configured for selectively rotating through said plurality of phase shifted divide-by-N clocks based on a constant phase shift interval, wherein said rotator unit controls a clock selection unit to produce a single output phase selected from said plurality of phase shifted divide-by-N clocks.