| 摘要 |
A semiconductor integrated circuit, operable in a normal mode and a test mode, includes a demodulator, a demodulated signal processing section, a header analysis section, a payload processing section, and a control section. The demodulator demodulates a modulated wireless signal including a synchronization pattern, header, and payload, to generate a demodulated signal. The demodulated signal processing section detects the synchronization pattern from the demodulated signal, generates a synchronization detection signal synchronized to the synchronization pattern, and converts the demodulated signal into a received bit sequence. The header analysis section extracts and analyzes the header to obtain the number of bits of the payload. The payload processing section processes the payload. The control section disables the demodulator when processing of the number of bits in the payload is completed in the normal mode, and disables the demodulator synchronously with a signal indicating the end of a test in the test mode. |
| 主权项 |
1. A semiconductor integrated circuit which is operable in a normal mode to perform a normal wireless communication and in a test mode, the semiconductor integrated circuit comprising:
a demodulator configured to demodulate a modulated wireless signal including a synchronization pattern, a header, and a payload, to generate a demodulated signal; a demodulated signal processing section configured to detect the synchronization pattern from the demodulated signal, generate a synchronization detection signal synchronized to the synchronization pattern, and convert the demodulated signal into a received bit sequence; a header analysis section configured to extract and analyze the header from the received bit sequence to obtain the number of bits of the payload; a payload processing section configured to process the payload; and a control section configured to disable the demodulator in the normal mode when the processing of the payload is completed according to the number of bits of the payload extracted by the header analysis section, and disable the demodulator in the test mode synchronously with a control signal indicating the end of a test. |
