| 发明名称 |
CLOCK SPURS REDUCTION TECHNIQUE |
| 摘要 |
Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency. The jitter of the controlled characteristic adjusts a clock harmonic at the radio frequency of the transceiver. |
| 申请公布号 |
US2015035576(A1) |
申请公布日期 |
2015.02.05 |
| 申请号 |
US201414519671 |
申请日期 |
2014.10.21 |
| 申请人 |
MARVELL WORLD TRADE LTD |
发明人 |
ROMANO Luca |
| 分类号 |
H03K5/13;H03K5/135 |
主分类号 |
H03K5/13 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A circuit comprising:
a jittered clock generator configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency, the jitter of the controlled characteristic adjusting a clock harmonic at the radio frequency of the transceiver. |
| 地址 |
St. Michael BB |
