SEMICONDUCTOR INTEGRATED CIRCUIT AND CLOCK SYNCHRONIZATION METHOD

摘要

According to the present invention, provided are a semiconductor integrated circuit and a clock synchronization method to reduce skew between multiple clocks having different power voltages applied to multiple semiconductor chips and to minimize the area of a clock synchronization circuit by securing rough synchronization using an oscillating signal. A semiconductor system according to the present invention includes: a first semiconductor chip which operates according to a first output clock transiting from a first level voltage to a second level voltage; a second semiconductor chip which operates according to a second output clock transiting from a third level voltage to a forth level voltage; and a clock synchronizer which receives the first output clock and the second output clock and synchronizes the phase of the first output clock with the phase of the second output clock to output the same. The clock synchronizer can secure synchronization by using an oscillating signal.