Silicon on insulator and thin film transistor bandgap engineered split gate memory

摘要

Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

主权项

1. A method for forming a semiconductor structure, comprising:
forming a plurality of first parallel semiconductor body regions with a first dopant type over a substrate; forming a plurality of first parallel word lines between a first select line and a second select line, the first word lines, the first select line and the second select line being over and intersecting the first semiconductor body regions in an array of cross points; forming a first tunneling barrier, a first charge storage layer and a first dielectric layer between the first semiconductor body regions and the first word lines; forming first dielectric spacers on a sidewall of the first select line and a sidewall of the second select line; forming first source/drain (S/D) junctions with a second dopant type adjacent to the first select line and the second select line; forming a second dielectric layer over the first word lines; forming a plurality of second parallel semiconductor body regions with the first dopant type over the second dielectric layer; forming a plurality of second parallel word lines between a third select line and a fourth select line, the second parallel word lines, the third select line and the fourth select line being over and substantially perpendicular to the second semiconductor body regions; forming a second tunneling barrier, a second charge storage layer and a third dielectric layer between the second semiconductor body regions and the second word lines; forming second dielectric spacers on a sidewall of the third select line and a sidewall of the fourth select line; and forming second source/drain (S/D) regions with the second dopant type adjacent to the third select line and the fourth select line; wherein the regions in the first semiconductor body regions between two neighboring first word lines and the regions in the second semiconductor body regions between two neighboring second word lines are junction-free.