INTEGRAL A/D CONVERTER AND CMOS IMAGE SENSOR

摘要

The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal; a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configured to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of clock signals when the output of the delay adjustment circuit is inverted and output the latched and decoded result as a low-order bit, wherein the TDC starts an operation thereof by the inversion of the comparison signal, and stops the operation thereof by the inversion of the output signal of the delay adjustment circuit.

主权项

1. An integral type Analog/Digital (AD) converter comprising:
a comparator configured to compare a reference voltage of a ramp waveform linearly changed according to a passing of time with an input voltage and output a comparison signal for the reference voltage and the input voltage; a multi-phase clock generation circuit configured to generate a plurality of clock signals including a main clock signal and clock signals having phases different from that of the main clock signal; a delay adjustment circuit configured to delay the comparison signal output from the comparator by a time period longer than one period of the main clock signal, and output the delayed comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit, based on the signals output from the delay adjustment circuit and the main clock signal, and output the counted result as a high order bit; and a time to digital converter configured to latch the plurality of clock signals generated by the multi-phase clock generation circuit at a time point when the output signal of the delay adjustment circuit is inverted and output a result obtained by decoding the corresponding latched value as a low-order, wherein the time to digital converter starts an operation thereof at the time point when the comparison signal output from the comparator is inverted, and stops the operation thereof after the low-order bit is output at the time point when the output signal of the delay adjustment circuit is inverted.