| 摘要 |
A memory according to an embodiment of the present invention includes a memory cell array. Word lines are connected to memory cells. Each of a plurality of bit lines is connected to one end of respective current paths of the memory cells. A sense amplifier is connected to the plurality of bit lines. A data write operation includes a first write loop and a second write loop. The first write loop includes a first program operation and a first verify operation. The second write loop includes a second program operation and a second verify operation. In the first verify operation, the sense amplifier discharges the voltage of at least one of the plurality of bit lines. In the second verify operation, the sense amplifier retains the voltages of the plurality of bit lines. |
