| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce a chip area by executing an operation to setting the memory cell to the erasing condition and then latching bit by bit for the over-writing at the time of sequentially assigning the gray code of n bits to the K threshold voltages and then writing the n-bit data to the memory cell. SOLUTION: A threshold voltage is set to Vt1 to Vt4 of 4 or higher, 3 to 3.5, 2 to 2.5, 1 to 1.5V and the information of 4 values, namely, 2 bits is stored in one memory cell. Moreover, the gray codes consisting of 00, 01, 11, 10 are sequentially assigned to Vt1 to Vt4. A threshold voltage control circuit VD- CNTRL controls the bit line voltage with an LATCH circuit group and a buffer circuit group BUF to judge completion of write/erase operation. Moreover, these simplified circuits are capable of reading and writing operations during mutual conversion between the binary level and multi-level signals. Thereby, the number of bits of the memory chip can be increased not depending on micro-miniaturization.</p> |
