发明名称 Conductive via hole and method for forming conductive via hole
摘要 Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
申请公布号 US8927433(B2) 申请公布日期 2015.01.06
申请号 US201012969469 申请日期 2010.12.15
申请人 Electronics and Telecommunications Research Institute 发明人 Kang Jin-Yeong
分类号 H01L21/311;H01L21/768;H01L21/288;H01L23/48 主分类号 H01L21/311
代理机构 代理人
主权项 1. A method for forming a conductive via hole, the method comprising: filling inside of a via hole structure that is formed in an upper portion of a substrate with silver by using a reduction and a precipitation of the silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing silver, on an upper layer inside of the via hole structure filled with the silver.
地址 Daejeon KR