8T NVSRAM cell and cell operations

摘要

One or more embodiments of 8T NVSRAM cell are provided for improving NVSRAM memory architecture with reduced cell size as opposed to the prior art of 12T NVSRAM cell. This novel 8T NVSRAM cell uses one step Write operation under either a FN-channel write scheme to increase a paired flash transistor Vt values in positive direction with a desired ΔVt12 ≧1V or a FN-edge write scheme to decrease the Vt values in negative direction with a similar desired ΔVt12≧1V to write the ΔVt12 into the paired flash transistors within 1-10 ms without requiring a pre-erase step. There is no need of Program-Inhibit Voltage (SBPI) to inhibit non-select flash transistor from programming. In addition, this 8T NVSRAM cell uses DRAM-like charge-sensing scheme to detect the ΔV on Q and QB nodes of SRAM in which is coupled and generated from the ΔVt12 stored in MC1 and MC2 flash transistors.

主权项

1. An 8T NVSRAM memory cell circuit with DRAM-like charge-sensing scheme, the 8T NVSRAM memory cell comprising:
a SRAM cell comprising two inverters cross-coupled to a first pass transistor and a second pass transistor commonly gated by a first word line and respectively coupled drains to a first bit line and a second bit line and sources to a first data node and a second data node, the first data node and the second data node respectively being outputted from the two invertors, each inverter including a PMOS device connected to a first power line and a NMOS device connected to a second power line, the first power line and the second power line being operated between a VDD power supply and ground and being separated from a common Nwell node; and a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first cell string including a first Flash transistor having a first drain node and first source node, the second cell string including a second Flash transistor having a second drain node and a second source node, the first and the second Flash transistors being gated commonly by a second word line, the first drain node being connected to the first data node, the second drain node being connected to the second data node, the first source node and the second source node being floating; wherein the second word line is configured to ramp up to a voltage level sufficient to detect as small as 1V threshold level difference between the first Flash transistor and the second Flash transistor and pass a voltage level difference to the first data node and the second data node, the two cross-coupled inverters are operated to amplify the voltage level difference to a scale of VSS=0V at one of the first data node and the second data node and the VDD level at another one of the first data node and the second data node.