发明名称 DATA TRANSFER DEVICE, BUFFERING CIRCUIT, AND BUFFERING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a data transfer device capable of storing data having a clock cycle shorter than a time for writing data to a memory.SOLUTION: A data transfer device 2 has a first bank 31 having a first bank first memory 311 and a first bank second memory 312, a second bank 32 having a second bank first memory 321 and a second bank second memory 322, and a control circuit 70. Each of the first bank 31 and the second bank 32 performs writing and reading in a reference cycle, and is alternately changed between a write state and a read state in an opposite phase to each other. The control circuit 60 performs control so that a data group to be input is sequentially stored in the first bank 31 and the second bank 32, and the stored data group is sequentially read.
申请公布号 JP2015001986(A) 申请公布日期 2015.01.05
申请号 JP20130124533 申请日期 2013.06.13
申请人 FUJITSU LTD 发明人 KITAHARA YOSHIHIRO
分类号 G11C7/00 主分类号 G11C7/00
代理机构 代理人
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