发明名称 |
Logic circuit and semiconductor integrated circuit |
摘要 |
Provided is a logic circuit that can reduce the variation of a power supply voltage supplied thereto and a semiconductor integrated circuit including the logic circuit. The logic circuit includes a buffer unit, a voltage detection unit, and a switch unit. The buffer unit is connected between a first power supply or a voltage regulator and a second power supply to receive power supply, and outputs a signal having the same or inverted logic level as an input signal to an output terminal. The voltage detection unit detects a voltage at the output terminal and outputs a detection signal based on a detection result. The switch unit connects the buffer unit to the first power supply or the voltage regulator in accordance with the detection signal. |
申请公布号 |
US8922241(B2) |
申请公布日期 |
2014.12.30 |
申请号 |
US201213610341 |
申请日期 |
2012.09.11 |
申请人 |
Renesas Electronics Corporation |
发明人 |
Urakawa Tatsuya |
分类号 |
H03K17/16;H03K19/003;H03K19/0175;H03K19/094 |
主分类号 |
H03K17/16 |
代理机构 |
Sughrue Mion, PLLC |
代理人 |
Sughrue Mion, PLLC |
主权项 |
1. A logic circuit comprising:
a buffer unit that is connected between a first power supply or a voltage regulator and a second power supply to receive power supply, and outputs a signal having the same or inverted logic level as an input signal to an output terminal; a voltage detection unit that detects a voltage at the output terminal and outputs a detection signal based on a detection result; and a switch unit that connects the buffer unit to the first power supply or the voltage regulator in accordance with the detection signal, wherein the voltage detection unit detects whether the voltage at the output terminal is a predetermined value or higher in a state where the buffer unit is connected to the first power supply, and when the voltage at the output terminal is the predetermined value or higher, the switch unit connects the buffer unit to the voltage regulator in accordance with the detection signal. |
地址 |
Kanagawa JP |