Virtual memory management to reduce address cache flushing during I/O operations

摘要

Approaches are described for reducing the number of memory address cache (e.g. TLB) flushes that need to be performed during the course of performing virtualized I/O. A device driver residing in a host domain registers a CPU that will be used for I/O processing and requests the hypervisor to pre-allocate a number of slots in the page tables to map memory pages during I/O operations. Upon receiving an I/O operation, when memory needs to be mapped, the driver provides the hypervisor with information about the registered CPU. The hypervisor uses the pre-allocated page table slots to create the new mapping and flushes the TLB cache corresponding to the CPU that will perform the I/O. The TLB cache belonging to other CPUs may not need to be flushed. The host driver ensures that the mapped memory page is used exclusively on the CPU or performs additional TLB flushes.

主权项

1. A computer implemented method for reducing translation lookaside buffer (TLB) flushes in a virtualized computing environment, said method comprising:
under the control of one or more computer systems configured with executable instructions, allocating one or more virtual memory buffers designated for a central processing unit (CPU) of a plurality of CPUs, each CPU being associated with a translation lookaside buffer (TLB), the one or more virtual memory buffers being allocated in a host domain for performing input/output (I/O) operations; receiving, by a driver in the host domain, a request to perform an I/O operation, the I/O operation associated with one or more physical memory buffers; selecting, by the driver in the host domain, the CPU for performing the I/O operation; requesting, by the driver in the host domain, a mapping of the one or more physical buffers to the one or more virtual buffers allocated for the selected CPU, the requesting indicating that the mapping should not cause a global flush of each TLB in the plurality of other CPUs; obtaining the mapping by the driver of the host domain; requiring that only the selected CPU accesses the one or more physical memory buffers associated with the I/O operation; and if a different CPU will be provided access to the one or more physical memory buffers associated with the I/O operation, requiring the different CPU first perform a flush of the TLB of the different CPU.