| 摘要 |
A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined. |
| 主权项 |
1. A semiconductor integrated circuit device comprising:
a main circuit having a first MISFET of a first channel type, a second MISFET of a second channel type different from the first channel type and a third MISFET of the second channel type which is connected in series with the second MISFET; and a control circuit which executes control so as to apply a first substrate bias voltage to the first MISFET and apply a second substrate bias voltage to the second MISFET and the third MISFET, wherein the control circuit comprises: a first delay circuit having a first inverter circuit including a fourth MISFET of the first channel type; a first current monitor circuit which includes a fifth MISFET of the first channel type, a sixth MISFET of the second channel type and a seventh MISFET of the second channel type connected in series with the sixth MISFET, and monitors a first current flowing through the fifth MISFET and a second current flowing through the sixth MISFET and the seventh MISFET; and a voltage generating circuit for generating the first substrate bias voltage and the second substrate bias voltage, and the control circuit makes the voltage generating circuit generate the first substrate bias voltage and apply it to the fourth MISFET, determines a first voltage value of the first substrate bias voltage based on a first delay time of the first delay circuit in a state where the first substrate bias voltage is being applied to the fourth MISFET, makes the voltage generating circuit generate the first substrate bias voltage set to the first voltage value and apply it to the fifth MISFET, acquires, by the first current monitor circuit, the first current flowing through the fifth MISFET in a state where the first substrate bias voltage set to the first voltage value is being applied thereto, makes the voltage generating circuit generate the second substrate bias voltage and apply it to the sixth MISFET and the seventh MISFET, acquires, by the first current monitor circuit, the second current flowing through the sixth MISFET and the seventh MISFET in a state where the second substrate bias voltage is being applied thereto, determines a second voltage value of the second substrate bias voltage based on the acquired first current and the acquired second current, and makes the voltage generating circuit generate the first substrate bias voltage set to the first voltage value and apply it to the first MISFET, and makes the voltage generating circuit generate the second substrate bias voltage set to the second voltage value and apply it to the second MISFET and the third MISFET. |
