Mesochronous signaling system with core-clock synchronization

摘要

In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

主权项

1. An integrated-circuit memory device comprising:
a clock input to receive a first clock signal from an external source; a signaling circuit to output a data signal from the integrated-circuit memory device in response to transitions of the first clock signal, wherein the first clock signal comprises a respective transition for each bit of data conveyed in the data signal; and a clock generating circuit to generate, in response to transitions of the first clock signal, a second clock signal that cycles once for every N cycles of the first clock signal, N being an integer greater than one, the clock generating circuit including phase-adjust circuitry to enable the phase of the second clock signal to be shifted relative to the phase of the first clock signal by a selected integer number of cycles of the first clock signal.