Multithreaded processor with multiple concurrent pipelines per thread

摘要

A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.

主权项

1. A multithreaded processor for processing a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor, comprising:
an instruction queue for N number of threads connected to a plurality of processor pipelines; issue circuitry connected to said instruction queue and comprising a thread switching circuit configured to:
determine a triggering event, said triggering event being one of a series of triggering events occurring on each processor clock cycle and separately associated with different ones of the threads; andcause the multithreaded processor to switch from a current thread of the N threads to a separate thread of the N threads upon each occurrence of said triggering event, said thread switching circuit comprising a register wherein the register stores a value identifying a next thread permitted to issue instructions; an execution data path configured to process a first instruction of a first type having a computation cycle comprising M number of stages, which is greater than the N number of threads; wherein the thread switching circuit is further configured to iteratively switch the multithreaded processor to process a single instruction from each of the remaining N threads in a predetermined order upon subsequent occurrences of the triggering event; wherein, after processing from each of the remaining N threads, the thread switching circuit is further configured to process a second instruction of the first type from the first thread; and wherein the number of stages M, number of threads N, and the location of register write back and read stages in the execution data path are configured such that results for the first instruction are always written to a register file before the results are needed by the second instruction without stalling the second instruction and without dependency checking and bypassing hardware.