发明名称 |
Insulating Layer for Planarization and Definition of the Active Region of a Nanowire Device |
摘要 |
Various embodiments include methods of fabricating a semiconductor device that include forming a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core, forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface, removing a portion of the insulating material layer to define an active region of nanowires, and forming an electrical contact over the substantially planar top surface of the insulating material layer. |
申请公布号 |
US2014367638(A1) |
申请公布日期 |
2014.12.18 |
申请号 |
US201414306563 |
申请日期 |
2014.06.17 |
申请人 |
Glo AB |
发明人 |
Herner Scott Brad |
分类号 |
H01L33/06;H01L21/02;H01L33/00 |
主分类号 |
H01L33/06 |
代理机构 |
|
代理人 |
|
主权项 |
1. A method of fabricating a semiconductor device, comprising:
forming a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core; forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface; removing a portion of the insulating material layer to define an active region of nanowires; and forming an electrical contact over the substantially planar top surface of the insulating material layer. |
地址 |
Lund SE |