HIGH-FREQUENCY SIGNAL PROCESSING DEVICE

摘要

Disclosed is a high-frequency signal processing device capable of reducing transmission power variation and harmonic distortion. For example, the high-frequency signal processing device includes a pre-driver circuit, which operates within a saturation region, and a final stage driver circuit, which operates within a linear region and performs a linear amplification operation by using an inductor having a high Q-value. The pre-driver circuit suppresses the amplitude level variation of a signal directly modulated, for instance, by a voltage-controlled oscillator circuit. Harmonic distortion components (2HD and 3HD), which may be generated by the pre-driver circuit, are reduced, for instance, by the inductor of the final stage driver circuit.

主权项

1. A high-frequency signal processing device comprising:
a first amplifier circuit which inputs a first differential signal and outputs a second differential signal; and a second amplifier circuit which inputs the second differential signal through a capacitor and outputs a third differential signal to an antenna; wherein the first amplifier circuit includes: a first MISFET and a second MISFET which operate by using the first differential signal as a gate input; a third MISFET which is coupled to a common source node for the first and second MISFETs and supplies a bias current to the first and second MISFETs; and a first inductor and a second inductor which are respectively coupled to the drains of the first and second MISFETs and operate as a load, wherein the second amplifier circuit includes: a fourth MISFET and a fifth MISFET which operate by using the second differential signal as a gate input; a sixth MISFET and a seventh MISFET which are configured so that the sources thereof are respectively coupled to the drains of the fourth and fifth MISFETs while a fixed voltage is applied to the gates of the sixth and seventh MISFETs; a third inductor and a fourth inductor which are respectively coupled to the drains of the sixth and seventh MISFETs and operate as a load; and an eighth MISFET which is configured so that the gate and drain thereof are coupled to a common electrode while the gate is coupled to the gates of the fourth and fifth MISFETs through a resistive element to supply a bias current to the fourth and fifth MISFETs, wherein the first and second MISFETs are larger in transistor size than the fourth and fifth MISFETs; wherein the bias currents flowing respectively to the first and second MISFETs are smaller than the bias currents flowing respectively to the fourth and fifth MISFETs, and wherein the third and fourth inductors have a higher Q-value than the first and second inductors.