Clock data recovery circuit with hybrid second order digital filter having distinct phase and frequency correction latencies

摘要

A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.

主权项

1. A clock data recovery apparatus for extracting successive bit data values from a serial bit data stream encoded with level transitions occurring between at least some successive bits in the bit data values, the level transitions conforming to a transmit frequency and a transmit phase position, the apparatus comprising:
a controllable oscillator producing a regenerated clock signal having level transitions within a controllable frequency range encompassing the transmit frequency, wherein the controllable oscillator is responsive to a control input; a phase detector operable to detect a timing relationship between the level transitions of the regenerated clock signal received at the phase detector versus the level transitions occurring between the bit data values received at the phase detector, the phase detector producing an output representing a phase timing difference between the serial data stream and the controllable oscillator; a feedback control having an output coupled to the control input of the controllable oscillator and having two feedback loops respectively configured to minimize phase and frequency error; wherein at least the feedback loop for minimizing said frequency error operates on a succession of multiple cycles of the regenerated clock representing multiple bits of the successive bits in the bit data values; and, wherein the feedback loop for minimizing said phase error operates on individual cycles of the regenerated clock, whereby the clock data recovery apparatus has a shorter feedback control latency for phase than for frequency.