发明名称 Switch block circuit in field programmable gate array
摘要 A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.
申请公布号 US8890570(B2) 申请公布日期 2014.11.18
申请号 US201213607637 申请日期 2012.09.07
申请人 Electronics and Telecommunications Research Institute 发明人 Cho Han Jin;Bae Young Hwan
分类号 H01L25/00;H03K19/173;G11C5/06 主分类号 H01L25/00
代理机构 代理人
主权项 1. A switch block circuit in a field programmable gate array, comprising: a configuration memory unit including first group memories and second group memories; a switching unit including first group switching transistors respectively switched depending on values stored in the first group memories, and second group switching transistors respectively switched depending on values stored in the second group memories and an operation mode; and a selection unit connected to outputs of the second group memories and to inputs of the second group switching transistors, and configured to correspondingly connect the outputs of the second group memories with the inputs of the second group switching transistors according to the operation mode, wherein the selection unit includes second group multiplexers responding to a selection control signal applied according to the operation mode.
地址 Daejeon KR
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