ADAPTIVE INTERFACE FOR COUPLING FPGA MODULES

摘要

A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA, whereby a serial interface is formed between the at least one FPGA and the at least one I/O module, comprising the steps of configuring a maximum number of registers to be transmitted for each FPGA application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.

主权项

1. A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as a corresponding sender side or receiver side, for connection to the FPGA, wherein a serial interface is formed between the at least one FPGA and the at least one I/O module, the method comprising:
configuring a maximum number of registers to be transmitted for each FPGA application; configuring a shared and/or fixed register width for all registers; setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted; transmitting an enable signal from the sender side to the receiver side; and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.