Implementing storage adapter performance optimization with parity update footprint mirroring

摘要

A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.

主权项

1. A data storage system comprising:
a first controller and a second controller, each of the first controller and the second controller comprising a plurality of hardware engines; a control store configured to store parity update footprint (PUFP) data; a data store; a nonvolatile random access memory (NVRAM); one of the first controller or the second controller operating in a first initiator mode builds a PUFP data frame for transferring PUFP data to the other of the first controller or the second controller operating in a target mode; respective initiator hardware engines transferring PUFP data from the initiator control store, and updating PUFP data, writing PUFP data to the initiator data store and the initiator NVRAM, and transmitting PUFP data to the other of the first controller or the second controller operating in the target mode; and respective target hardware engines writing PUFP data to the target data store and the target NVRAM, eliminating firmware operations.