发明名称 Variable length code decoding device and decoding method
摘要 Variable length code decoding device for decoding variable length code data, including: decoding process tables each including at least two kinds of formats consisting a first format storing identification information for designating a subsequent table to be referred to in a subsequent decoding process, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data. The device utilizes first, second, third and fourth formats and relative addresses.
申请公布号 US8884792(B2) 申请公布日期 2014.11.11
申请号 US201213602360 申请日期 2012.09.04
申请人 Renesas Electronics Corporation 发明人 Nakata Hiroaki;Izuhara Fumitaka;Akie Kazushi;Yuasa Takafumi
分类号 H03M7/40;H03M7/42;H04N19/176;H03M7/30;H04N19/61;H03M7/46 主分类号 H03M7/40
代理机构 Antonelli, Terry, Stout & Kraus, LLP. 代理人 Antonelli, Terry, Stout & Kraus, LLP.
主权项 1. A variable length code decoding method for decoding variable length code data, comprising: decoding process tables each including at least two kinds of formats consisting a first format that stores identification information for designating a subsequent table to be referred to in a decoding process which is subsequently executed, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data, wherein the data that is stored in the respective entries of the decoding process table is described in any one of at least two kinds of formats consisting of the first format and the second format; the two kinds of formats are stored in a memory device where the stored location of the data can be designated by an address; the decoding process tables to be referred to in the decoding process are made of using a plurality of the two kinds of formats; the identification information designating the subsequent table included in the first format indicates a start address of the subsequent table with a relative address; an address being a standard of the relative address is an address next to the last entry in the decoding process table which includes an entry storing the relative address as a component; a third format having an address that stores the decoded value instead of the previous decoded value when a value which exceeds an expressible bit length is determined to be a decoded value in a portion allocated to a decoded value of the second format; a fourth format being an entry format for a portion indicated by an address stored in the third format is further provided; the decoded value is stored in the fourth format, an address stored in the third format is indicated by the relative address; and an address being a standard of the relative address is an address next to a last entry in the decoding process table which includes the entry storing the relative address as a component.
地址 Kanagawa JP