发明名称 PLANAR TRANSISTORS WITH NANOWIRES COINTEGRATED ON A SOI UTBOX SUBSTRATE
摘要 Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.
申请公布号 US2014326955(A1) 申请公布日期 2014.11.06
申请号 US201414266999 申请日期 2014.05.01
申请人 COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ;STMICROELECTRONICS (CROLLES 2) SAS 发明人 BARRAUD Sylvain;MORAND Yves
分类号 H01L27/12;H01L29/51;H01L29/06;H01L21/84;H01L29/78 主分类号 H01L27/12
代理机构 代理人
主权项 1. A method for making a microelectronic device including steps as consisting of: a) making one or several semiconducting bars, designed to form at least one transistor channel or several transistor channels of a first type in a first region of a thin semiconducting layer of a substrate facing an opening in a first mask, said substrate being a semiconductor on insulator type substrate comprising a support layer on which an insulating layer is supported, said thin semiconducting layer being supported on said insulating layer, b) removing an area from the insulating layer in extension of said opening in said first mask so as to expose said semiconducting bars. c) replacing said area removed from said insulating layer by a given dielectric material with a composition and a thickness selected to facilitate capacitive coupling between said support layer and said conducting bar(s).
地址 Paris FR