Line-edge roughness improvement for small pitches

摘要

A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional overetch percentage; removing the SiON film layer immediately after completion of the amorphous carbon film layer etching; and lowering the lower electrode temperature below a conventional temperature.

主权项

1. A method for fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate with a plurality of mask layers formed on the semiconductor substrate, wherein the plurality of mask layers comprise: an organic antireflective coating/silicon oxynitride (oARC/SiON) film stack for mitigating line-edge roughness in the semiconductor device; providing a patterned photoresist layer over the plurality of mask layers formed over the substrate, wherein the patterned photoresist layer is in contact with the oARC/SiON film stack; and etching the plurality of mask layers formed on the substrate, using the patterned photoresist layer as an etching mask to form at least one trench in the plurality of mask layers, wherein the oARC/SiON film stack is etched with an overetch that is less than 30 percent, wherein the overetch of less than 30 percent prevents resulting increase in top and bottom line width roughness while cleaning out the SiON, and wherein a higher percentage of SiON overetch provides undesirable increase in to and bottom average line width roughness.