Data process for E-beam lithography

摘要

The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

主权项

1. A method comprising:
receiving an integrated circuit (IC) design layout; generating a vertex information from the IC design layout; generating a gray map from the IC design layout, wherein the gray map is generated based on the vertex information; generating an edge map from the IC design layout, wherein the edge map is generated based on the vertex information; and modifying the IC design layout based on the gray map and the edge map.