System and methods for converting planar design to FinFET design

摘要

A method and layout generating machine for generating a layout for a device having FinFETs from a first layout for a device having planar transistors are disclosed. A planar layout with a plurality of FinFET active areas is received and corresponding FinFET active areas are generated with active area widths. Mandrels are generated according to the active area widths and adjusted such that a beta ratio of a beta number for each FinFET active area to a beta number for each corresponding planar active area is within a predetermined beta ratio range.

主权项

1. A method of generating a FinFET structure layout performed by a layout generating machine having a processor component executing instructions, the method comprising:
receiving a planar structure layout for an integrated circuit (IC) design, the planar structure layout including a plurality of planar active areas; generating a plurality of FinFET active areas corresponding to the plurality of planar active areas; generating mandrels in a FinFET active area of the plurality of FinFET active areas according to a FinFET active area width; determining a beta number for the FinFET active area of the plurality of FinFET active areas; determining a beta number for a planar active area of the plurality of planar active areas corresponding to the FinFET active area of the plurality of FinFET active areas; and adjusting the mandrels in the FinFET active area of the plurality of FinFET active areas such that a beta ratio of the FinFET active area beta number to the planar active area beta number is within a predetermined beta ratio range.