Method and apparatus of power management of processor

摘要

A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.

主权项

1. A computer-implemented method, comprising:
setting an upper performance state limit and a lower performance state limit, the upper performance state limit based on a processor activity rate value and the lower performance state limit based on a minimum requirement of an operating system to perform tasks; adjusting the upper performance state limit when the processor activity rate value is above an upper threshold value for the upper performance state limit or below a lower threshold value for the upper performance state limit; and adjusting the lower performance state limit when the processor activity rate value is above an upper threshold value for the lower performance state limit or below a lower threshold value for the lower performance state limit; setting a performance state value to the upper performance state limit; setting the upper performance state limit within the upper and lower threshold values set for the upper performance state limit; monitoring the processor activity over a predetermined time interval; calculating the processor activity rate value; comparing the upper and lower threshold values set for the upper performance state limit to the processor activity rate; increasing the upper performance state limit when the processor activity rate is above the upper threshold value set for the upper performance state limit; and decreasing the upper performance state limit when the processor activity rate is below the lower threshold value set for the upper performance state limit.