| 摘要 |
<p>An SOI substrate is covered with an etching mask defining three separate semiconductor patterns. A lateral spacer (11) is formed around these three patterns and two adjacent patterns are connected together. The buried insulating layer is removed so as to define a cavity that suspends a portion of a first pattern. The first etching mask is removed. A gate dielectric is formed on two opposite main faces of the first pattern. A resist is deposited in the cavity and on the first pattern, which resist is then exposed to form two patterns defining lower and upper gates. An electrically conductive material (14) is deposited in the cavity and on the first pattern so as to form the lower gate and the upper gate on either side of the first semiconductor pattern.</p> |
