发明名称 SATURATION VOLTAGE ESTIMATION METHOD AND MANUFACTURING METHOD OF SILICON EPITAXIAL WAFER
摘要 <p>PROBLEM TO BE SOLVED: To provide a technique advantageous for fabricating with high production yield a semiconductor device from a silicon epitaxial wafer in which an epitaxial layer has a carbon concentration of 5×10atoms/cmor less.SOLUTION: Carbon contained in an epitaxial layer of a silicon epitaxial wafer is emission-activated, the emission-activated carbon is caused to emit light, and an emission intensity or an intensity ratio deriving from the carbon is determined. The relation between the intensity or the intensity ratio and a collector-emitter saturation voltage is checked in advance. A part of wafers are picked up from a production lot of the silicon epitaxial wafers, and the emission intensity or the intensity ratio of the wafers is determined. Referring the intensity or the intensity ratio to the aforementioned relation, it is determined whether the production lot is acceptable.</p>
申请公布号 JP2014199253(A) 申请公布日期 2014.10.23
申请号 JP20140044619 申请日期 2014.03.07
申请人 GLOBALWAFERS JAPAN CO LTD 发明人 NAKAGAWA SATOKO;KASHIMA KAZUHIKO
分类号 G01N21/64;H01L21/336;H01L21/66;H01L29/739;H01L29/78 主分类号 G01N21/64
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