Memory device and liquid crystal display device equipped with memory device

摘要

A transistor (N1) has a gate terminal connected to a word line (Xi(1)) and a first conduction terminal connected to a bit line (Yj). A transistor (N2) has a gate terminal connected to the word line (Xi(2)) and a first conduction terminal connected to a node (PIX). A transistor (N3) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi(2)). A transistor (N4) has a gate terminal connected to the word line (Xi(3)), a first conduction terminal connected to a second conduction terminal of the transistor (N3), and a second conduction terminal connected to the node (PIX). Capacitors (Ca1), (Cb1), (Cap1) are formed between the node (PIX) and a reference electric potential wire (RL1), between the node (MRY) and the reference electric potential wire (RL1), and between the first conduction terminal of the transistor (N3) and the node (MRY), respectively.

主权项

1. A memory-type liquid crystal display device which carries out a refresh operation in a data retention period following writing of a data signal electric potential, comprising:
data signal lines; scanning signal lines; retention capacitor wires; data transfer lines; refresh lines; pixel electrodes; a counter electrode; first transistors; second transistors; third transistors; fourth transistors; first capacitors; second capacitors; and third capacitors, wherein each pixel electrode is associated with the first transistors, the second transistors, the third transistors, the fourth transistors, the first capacitors, the second capacitors, and the third capacitors in such a manner that (i) a first transistor associated with the pixel electrode has a control terminal which is connected to a scanning signal line associated with the pixel electrode, (ii) a second transistor associated with the pixel electrode has a control terminal which is connected to a data transfer line associated with the pixel electrode, (iii) a third transistor associated with the pixel electrode has a control terminal which is connected to the pixel electrode via the second transistor, (iv) a fourth transistor associated with the pixel electrode has a control terminal which is connected to a refresh line associated with the pixel electrode, (v) a first capacitor associated with the pixel electrode is connected to the pixel electrode, (vi) a second capacitor associated with the pixel electrode is connected to the pixel electrode via the second transistor, (vii) a third capacitor associated with the pixel electrode is formed between (a) a conduction terminal of the third transistor which conduction terminal is connected to the data transfer line and (b) the control terminal of the third transistor, and (viii) the pixel electrode is connected to a data signal line associated with the pixel electrode via the first transistor and is connected to the data transfer line via the fourth transistor and the third transistor, wherein in a writing period in which the data signal electric potential is written, the data transfer lines are kept active, wherein the scanning signal lines are sequentially selected while supplying the data signal electric potential to the data signal lines, and in the data retention period, a constant electric potential which turns the third transistors on is supplied to the data signal lines.