Single layer coreless substrate

摘要

An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages.

主权项

1. An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer, wherein the via post layer includes via posts embedded in a dielectric material comprising glass fibers in a polymer resin, and the chip and routing layer are embedded in a second layer of dielectric material encapsulating the chip and the routing layers and wherein an underside of the interposer includes copper ends of via posts surrounded with the dielectric material such that the copper ends of the via posts are flush with the dielectric material.