发明名称 |
Semiconductor apparatus with open bit line structure |
摘要 |
A semiconductor apparatus with an open bit line structure includes a memory bank including a plurality of memory cell blocks and dummy mats, in which a plurality of bit lines are formed, a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference, and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode. |
申请公布号 |
US8867282(B2) |
申请公布日期 |
2014.10.21 |
申请号 |
US201113339183 |
申请日期 |
2011.12.28 |
申请人 |
SK Hynix Inc. |
发明人 |
Yun Tae Sik;Park Kee Teok |
分类号 |
G11C7/00;G11C29/00;G11C29/24;G11C11/4099;G11C29/12;G11C11/401 |
主分类号 |
G11C7/00 |
代理机构 |
William Park & Associates Patent Ltd. |
代理人 |
William Park & Associates Patent Ltd. |
主权项 |
1. A semiconductor apparatus with an open bit line structure, comprising:
a memory bank including a plurality of memory cell blocks and dummy mats, wherein a plurality of bit lines are formed in the plurality of memory cell blocks and dummy mats; a bit line sense amplifier configured to be arranged between the plurality of memory cell blocks and the dummy mats, compare a voltage difference between a bit line and a complementary bit line, and amplify the difference; and a dummy word line driving unit configured to selectively activate a dummy word line of the dummy mat in response to a test mode, wherein, when a test operation is performed with respect to the semiconductor apparatus, the dummy word line driving unit deactivates a dummy word line signal and applies a deactivated dummy word line signal to the dummy mat, wherein the dummy word line driving unit comprises: a complementary dummy word line signal generation section configured to generate a preliminary complementary dummy word line signal in response to a plurality of test mode signals; a level shifter section configured to shift a level of the preliminary complementary dummy word line signal, which is output from the complementary dummy word line signal generation section, and generate a complementary dummy word line signal; and a driving section configured to invert a level of the complementary dummy word line signal, which is output from the level shifter section, and generate a dummy word line signal. |
地址 |
Gyeonggi-do KR |