| 摘要 |
The objective of the present invention is to reduce a bezel width of a display device by a layout design of a gate driver. Two gate drivers are installed on the left and right of a pixel unit, respectively. Gate lines are alternately connected to left and right gate drivers at every M rows. The two gate drivers have a shift register and a demultiplexer configured by a single conductivity type transistor. The shift register has k number of first unit circuits that are cascade-connected. The demultiplexer receives a signal from the first unit circuit and has k number of second unit circuits to which M number of gate lines are connected. The second unit circuit selects, from the M number of the gate lines, one or more lines through which an input signal from the first unit circuit is outputted, and outputs the signal from the first unit circuit to the selected line. Since a gate signal can be outputted to the M number of the gate lines from an output of a 1-stage shift register, the width of the shift register can be reduced. |
