发明名称 |
Oxide stress reduction for a cascode stack circuit |
摘要 |
A reduced oxide stress cascode stack circuit includes a cascade transistor stack and dynamic bias circuits that supply an output voltage having a magnitude greater than an oxide reliability voltage of their component transistors. The reduced oxide stress cascode stack circuit also includes an offset voltage generator that provides an offset voltage based on a transient extreme of the output voltage, wherein the offset voltage is applied to the cascade transistor stack and the dynamic bias circuits to reduce component transistor voltages commensurate with the oxide reliability voltage. The reduced oxide stress cascode stack circuit further includes a bias voltage supply that modifies a bias voltage value of the cascade transistor stack and dynamic bias circuits by an amount proportional to the offset voltage. A method of reducing oxide stress in a cascode stack circuit is also provided. |
申请公布号 |
US8860497(B1) |
申请公布日期 |
2014.10.14 |
申请号 |
US201313932890 |
申请日期 |
2013.07.01 |
申请人 |
Nvidia Corporation |
发明人 |
Pattnayak Tapan;Yu Shifeng |
分类号 |
G05F1/10;H02M3/04 |
主分类号 |
G05F1/10 |
代理机构 |
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代理人 |
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主权项 |
1. A reduced oxide stress cascode stack circuit, comprising:
a cascade transistor stack and dynamic bias circuits that supply an output voltage having a magnitude greater than an oxide reliability voltage of their component transistors; an offset voltage generator that provides an offset voltage based on a transient extreme of the output voltage; and a bias voltage supply that modifies a bias voltage value of the cascade transistor stack and the dynamic bias circuits, wherein the offset voltage is applied to the cascade transistor stack and the dynamic bias circuits to reduce component transistor voltages commensurate with the oxide reliability voltage. |
地址 |
Santa Clara CA US |