Clock driver for frequency-scalable systems

摘要

A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.

主权项

1. An apparatus comprising:
a delay circuit coupled to receive an input clock signal and supply a delayed clock signal; a first transistor coupled to receive a first pulse control signal as a first gate signal and supply an output clock node to generate an output clock signal based in part on the first pulse control signal, wherein an asserted edge of the first pulse control signal is responsive to a falling edge of the delayed clock signal; and a second transistor coupled to receive a second control signal as a second gate signal and to supply the output clock node to generate the output clock signal based in part on the second control signal, wherein an asserted edge of the second pulse control signal is responsive to a rising edge of the delayed clock signal, wherein the first and second pulse control signals are generated independently of the output clock signal; and wherein the first pulse control signal is deasserted responsive to a rising edge of the input clock signal and wherein the second pulse control signal is deasserted responsive to a falling edge of the input clock signal.