| 摘要 |
Disclosed is an FPGA phase comparator which is used for a PLL circuit. The FPGA phase comparator includes: a 1/2 divider which receives a feedback signal and divides the signal into two; a 1/8 divider which receives a local clock signal of 8,192 MHz and divides the signal into eight; a multiplexer which selects and outputs one from either the signal which is divided into eight in the 1/8 divider or a recovery clock signal which is also selected from either a recovery clock signal 1 or a recovery clock signal 4, which are 1,024 MHz; a 1/4 divider which receives a signal outputted by being selected in the multiplexer and divides the signal into four; and a phase comparator which has a 1/1 divider which receives the signal of 256 kHz divided into four in the 1/4 divider as a reference clock (REFCLK) and divides the signal into one, a 1/64 divider of dividing a signal into 64 by receiving the signal of 16,384 MHz divided into two in the 1/2 divider as an input signal, and outputs a phase equally by mutually comparing a phase difference between the reference clock signal divided into one in the 1/1 divider and the signal divided into 64 in the 1/64 divider. By the present invention, the FPGA phase comparator used for the PLL circuit can be manufactured easily and conveniently by forming the FPGA phase comparator to be composed of dividers and a multiplexer by using only a counter and a NAND gate. |
