Performing a cyclic redundancy checksum operation responsive to a user-level instruction

摘要

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a set of registers, including:
a first 32-bit register to store a first operand;a second 32-bit register to store a second operand;a first 64-bit register to store a third operand; anda second 64-bit register to store a fourth operand; a plurality of execution units to perform exclusive-OR (XOR) operations on data of a configurable size responsive to instructions of an instruction set architecture (ISA) for the processor, the plurality of execution units including:
a first execution unit coupled to the first and the second 32-bit registers to perform a first XOR operation on at least one bit of the first and the second operands and to store a result of the first XOR operation in a first destination register responsive to a first instruction of the ISA; anda second execution unit coupled to the first and the second 64-bit registers to perform a second XOR operation on at least one bit of the third and the fourth operands and to store a result of the second XOR operation in a second destination register responsive to a second instruction of the ISA; and a memory interface logic to provide access to an external memory.