| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor configured to improve throughput, while maintaining cache coherency.SOLUTION: When an invalidation request is input from the other processor, a cache controller (21) registers an invalidation request address of the invalidation request and a combination of identifiers of the other processor which has output the invalidation request, on an invalidation history tale (41). When a central processing unit (11) reads data of a first address which is not stored in a cache memory (31), the cache controller outputs a coherent read request including the first address to the other processor indicated by the identifier of the other processor which has output the invalidation request corresponding to the first address when the first address has been already registered on the invalidation history table. When the first address is not registered on the invalidation history table, the cache controller outputs the coherent read request including the first address to all the other processors. |
