| 摘要 |
<p>Systems and methods for correcting clock duty cycle and/or performing output delay adjustment are provided for application in serial- connected devices operating as slave devices. A master device provides a clock to the first slave device. Each slave device passes the clock to the next slave device in turn. The last slave device returns the clock to the master device. The master device compares the outgoing and returned clocks and determines if a duty cycle correction and/or an output delay adjustment is needed. If so, the master device generates and outputs commands for slave devices to perform duty cycle and/or output delay adjustment. The slave devices each have a circuit for performing duty cycle correction and/or output delay adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller.</p> |
